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commit    f9edfc1aa9ea4f0bae87eabcac261d82370c7de4
Author:   Andres Freund <andres@anarazel.de>
Date:     Fri Sep 19 15:04:00 2014 +0000
First released in: 9.5.0, 9.2.10, 9.3.6, 9.4.0

    Mark x86's memory barrier inline assembly as clobbering the cpu flags.
    
    x86's memory barrier assembly was marked as clobbering "memory" but
    not "cc" even though 'addl' sets various flags. As it turns out gcc on
    x86 implicitly assumes "cc" on every inline assembler statement, so
    it's not a bug. But as that's poorly documented and might get copied
    to architectures or compilers where that's not the case, it seems
    better to be precise.
    
    Discussion: 20140919100016.GH4277@alap3.anarazel.de
    
    To keep the code common, backpatch to 9.2 where explicit memory
    barriers were introduced.


 src/include/storage/barrier.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/include/storage/barrier.h b/src/include/storage/barrier.h
index bc61de0ff14..2bef2eb6ad9 100644
--- a/src/include/storage/barrier.h
+++ b/src/include/storage/barrier.h
@@ -75,7 +75,7 @@ extern slock_t dummy_spinlock;
  * "lock; addl" has worked for longer than "mfence".
  */
 #define pg_memory_barrier()		\
-	__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
+	__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory", "cc")
 #define pg_read_barrier()		pg_compiler_barrier()
 #define pg_write_barrier()		pg_compiler_barrier()
 #elif defined(__x86_64__)		/* 64 bit x86 */
@@ -89,7 +89,7 @@ extern slock_t dummy_spinlock;
  * do those things, a compiler barrier should be enough.
  */
 #define pg_memory_barrier()		\
-	__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory")
+	__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory", "cc")
 #define pg_read_barrier()		pg_compiler_barrier()
 #define pg_write_barrier()		pg_compiler_barrier()
 #elif defined(__ia64__) || defined(__ia64)


[parent: 78b488d2e3d8]