Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1tFbDo-00EBN5-Df for pgsql-bugs@arkaria.postgresql.org; Mon, 25 Nov 2024 15:41:56 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.94.2) (envelope-from ) id 1tFbDn-00FuE8-3V for pgsql-bugs@arkaria.postgresql.org; Mon, 25 Nov 2024 15:41:55 +0000 Received: from makus.postgresql.org ([2001:4800:3e1:1::229]) by malur.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1tFbDm-00FuDz-R6 for pgsql-bugs@lists.postgresql.org; Mon, 25 Nov 2024 15:41:54 +0000 Received: from sss.pgh.pa.us ([68.162.161.243]) by makus.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1tFbDk-003iJu-B3 for pgsql-bugs@lists.postgresql.org; Mon, 25 Nov 2024 15:41:53 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.15.2/8.15.2) with ESMTP id 4APFfbdg1346553; Mon, 25 Nov 2024 10:41:37 -0500 From: Tom Lane To: Thomas Munro cc: Heikki Linnakangas , =?UTF-8?Q?Bastien_Roucari=C3=A8s?= , pgsql-bugs@lists.postgresql.org Subject: Re: Detection of hadware feature => please do not use signal In-reply-to: <1229505.1732498033@sss.pgh.pa.us> References: <4496616.iHFcN1HehY@portable-bastien> <1156374.1730396928@sss.pgh.pa.us> <7ec1c65c-1a28-49a7-af43-f77c260a3df6@iki.fi> <1292593.1730399134@sss.pgh.pa.us> <707008.1732325995@sss.pgh.pa.us> <736756.1732341046@sss.pgh.pa.us> <865773.1732399354@sss.pgh.pa.us> <885805.1732406935@sss.pgh.pa.us> <1074317.1732479406@sss.pgh.pa.us> <1216860.1732491268@sss.pgh.pa.us> <1229505.1732498033@sss.pgh.pa.us> Comments: In-reply-to Tom Lane message dated "Sun, 24 Nov 2024 20:27:13 -0500" MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-ID: <1346551.1732549297.1@sss.pgh.pa.us> Date: Mon, 25 Nov 2024 10:41:37 -0500 Message-ID: <1346552.1732549297@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk I wrote: > I also confirmed that our existing code works on Fedora 30 armv7l > (also hard-float) with gcc 9.3.1. That's the only other ARM32 > image I have at hand :-( > So yeah, it would seem they broke it between 10.2.1 and 10.5.0. After discussion with the gcc folk (see bug report linked upthread) it emerges that there was indeed a change somewhere in that time frame. It used to be that if the platform defaults were "-march=A -mfpu=X" then writing "-march=B" on the command line would still leave you with "-mfpu=X", possibly a nonsensical combination. So now they ignore any build-time default, with the effect that writing just "-march=armv8-a+crc" selects soft float, which fails on platforms that require hard-float ABI. (I didn't ask whether this was the same change prompted by the other bug report you found, but perhaps it was.) Also, there's no +fp option for "-march=armv8-a" because the ARMv8 specs require chips to implement both or neither of FP and SIMD. So the idiomatic thing for us to write is not a separate -mfpu spec but "-march=armv8-a+crc+simd". I'll adjust my patch to do it like that and push later today. regards, tom lane