Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hcXq3-0004bB-Lw for pgsql-bugs@arkaria.postgresql.org; Sun, 16 Jun 2019 16:17:03 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.89) (envelope-from ) id 1hcXq0-00067C-M7 for pgsql-bugs@arkaria.postgresql.org; Sun, 16 Jun 2019 16:17:00 +0000 Received: from magus.postgresql.org ([2a02:c0:301:0:ffff::29]) by malur.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hcXq0-000675-EX for pgsql-bugs@lists.postgresql.org; Sun, 16 Jun 2019 16:17:00 +0000 Received: from sss.pgh.pa.us ([66.207.139.130]) by magus.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hcXpw-0002zf-MD for pgsql-bugs@lists.postgresql.org; Sun, 16 Jun 2019 16:16:59 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.14.4/8.14.4) with ESMTP id x5GGGrZa022616; Sun, 16 Jun 2019 12:16:53 -0400 From: Tom Lane To: YunQiang Su cc: pgsql-bugs@lists.postgresql.org Subject: Re: BUG #15844: MIPS: remove .set mips2 in s_lock.h to fix r6 build In-reply-to: References: <15844-8f62fe7e163939b3@postgresql.org> <15052.1560455595@sss.pgh.pa.us> <23287.1560655935@sss.pgh.pa.us> <25321.1560659282@sss.pgh.pa.us> Comments: In-reply-to YunQiang Su message dated "Sun, 16 Jun 2019 12:38:05 +0800" MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-ID: <22614.1560701813.1@sss.pgh.pa.us> Content-Transfer-Encoding: quoted-printable Date: Sun, 16 Jun 2019 12:16:53 -0400 Message-ID: <22615.1560701813@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Precedence: bulk YunQiang Su writes: > Tom Lane =E4=BA=8E2019=E5=B9=B46=E6=9C=8816=E6=97=A5= =E5=91=A8=E6=97=A5 =E4=B8=8B=E5=8D=8812:28=E5=86=99=E9=81=93=EF=BC=9A >> I found that specifying -march=3Dmips2 gets it to accept the s_lock.h >> code without ".set mips2". Given that we don't make any pretense of >> actually running on MIPS-I hardware, I wonder if some hack involving >> forcing -march would be sane? You'd get better code quality across >> the board, presumably. > -march is not a good idea, since r6 cannot compatible with the previous = version. > If you use -march=3Dmips2 or something else, it will failed to build for= r6. > Which -march to use should be determined by finial user or distribution = vendor. Sure, the trick would be to not override a (default or specified) architecture setting that's higher than mips2. I was imagining using AC_EGREP_CPP() to see if __mips expands to exactly 1. But on reflection, probably a better idea is to just see if asm with ll/sc/sync compiles, and add -march=3Dmips2 if not. (We should not do anything if --disable-spinlocks has been specified, btw, since then we don't need those asm commands to work. This is and would remain the workaround for building PG for MIPS-I, if some benighted soul insists on doing that.) >> (BTW, have you got any recommendations for booting recent Debian/MIPS >> under qemu? I can't get anything newer than wheezy to work.) > I have an r6 one: > http://mips64el.bfsu.edu.cn/debian-new/tarball/qemu/ > It is buster. Thanks for the pointer. regards, tom lane