Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rO2ph-000lSF-AP for pgsql-bugs@arkaria.postgresql.org; Thu, 11 Jan 2024 21:43:25 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.94.2) (envelope-from ) id 1rO2pg-00FNQK-DW for pgsql-bugs@arkaria.postgresql.org; Thu, 11 Jan 2024 21:43:24 +0000 Received: from magus.postgresql.org ([2a02:c0:301:0:ffff::29]) by malur.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rO2pg-00FNQC-5F for pgsql-bugs@lists.postgresql.org; Thu, 11 Jan 2024 21:43:24 +0000 Received: from sss.pgh.pa.us ([68.162.161.243]) by magus.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rO2pd-00153F-OM for pgsql-bugs@lists.postgresql.org; Thu, 11 Jan 2024 21:43:23 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.15.2/8.15.2) with ESMTP id 40BLhGml325299; Thu, 11 Jan 2024 16:43:16 -0500 From: Tom Lane To: Robert Haas cc: Alexander Lakhin , pgsql-bugs@lists.postgresql.org, Richard Guo , Andres Freund , Peter Geoghegan Subject: Re: BUG #17798: Incorrect memory access occurs when using BEFORE ROW UPDATE trigger In-reply-to: References: <17798-0907404928dcf0dd@postgresql.org> <87fe6c28-80b2-f709-a8db-d105e5240e39@gmail.com> <1849610.1682807087@sss.pgh.pa.us> <494cd7c4-c109-6886-c0e3-138a95e7e38b@gmail.com> <74335d44-819d-60e0-859a-efe74d9c84c2@gmail.com> Comments: In-reply-to Robert Haas message dated "Thu, 11 Jan 2024 09:34:56 -0500" MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-ID: <325297.1705009396.1@sss.pgh.pa.us> Content-Transfer-Encoding: quoted-printable Date: Thu, 11 Jan 2024 16:43:16 -0500 Message-ID: <325298.1705009396@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk Robert Haas writes: > On Wed, Jan 10, 2024 at 10:00=E2=80=AFPM Alexander Lakhin wrote: >> I was discouraged by that vast distance and implicit buffer usage too, = but >> I found no other feasible way to fix it. On the other hand, 75e03eabe a= nd >> Andres's words upthread made me believe that it's an acceptable solutio= n. > I agree that it's potentially acceptable. I just wonder if Tom or > someone else is going to want to propose a bigger change to avoid some > of this messiness. I don't know what that would look like, though. I'm still feeling itchy about it. Maybe the problem could be fixed better if we didn't re-use slots with such abandon in this code, but I don't have a concrete proposal. Also, that'd likely be a nontrivial rewrite bringing its own possibilities of adding bugs. Some concrete thoughts: * Maybe better to Assert(newslot =3D=3D epqslot_clean) instead of what you did here? Not sure. * Why is the ExecMaterializeSlot step needed if we don't have an epqslot_candidate? regards, tom lane