Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hcta5-0007A9-62 for pgsql-bugs@arkaria.postgresql.org; Mon, 17 Jun 2019 15:30:01 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.89) (envelope-from ) id 1hcta3-0007jR-OW for pgsql-bugs@arkaria.postgresql.org; Mon, 17 Jun 2019 15:29:59 +0000 Received: from magus.postgresql.org ([2a02:c0:301:0:ffff::29]) by malur.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hcta3-0007jK-GJ for pgsql-bugs@lists.postgresql.org; Mon, 17 Jun 2019 15:29:59 +0000 Received: from sss.pgh.pa.us ([66.207.139.130]) by magus.postgresql.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1hctZx-0007U5-15 for pgsql-bugs@lists.postgresql.org; Mon, 17 Jun 2019 15:29:59 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.14.4/8.14.4) with ESMTP id x5HFTnci003974; Mon, 17 Jun 2019 11:29:49 -0400 From: Tom Lane To: YunQiang Su cc: pgsql-bugs@lists.postgresql.org Subject: Re: BUG #15844: MIPS: remove .set mips2 in s_lock.h to fix r6 build In-reply-to: <22615.1560701813@sss.pgh.pa.us> References: <15844-8f62fe7e163939b3@postgresql.org> <15052.1560455595@sss.pgh.pa.us> <23287.1560655935@sss.pgh.pa.us> <25321.1560659282@sss.pgh.pa.us> <22615.1560701813@sss.pgh.pa.us> Comments: In-reply-to Tom Lane message dated "Sun, 16 Jun 2019 12:16:53 -0400" MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----- =_aaaaaaaaaa0" Content-ID: <3925.1560785347.0@sss.pgh.pa.us> Date: Mon, 17 Jun 2019 11:29:49 -0400 Message-ID: <3973.1560785389@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Precedence: bulk ------- =_aaaaaaaaaa0 Content-Type: text/plain; charset="us-ascii" Content-ID: <3925.1560785347.1@sss.pgh.pa.us> I wrote: > Sure, the trick would be to not override a (default or specified) > architecture setting that's higher than mips2. I was imagining > using AC_EGREP_CPP() to see if __mips expands to exactly 1. But > on reflection, probably a better idea is to just see if asm with > ll/sc/sync compiles, and add -march=mips2 if not. Concretely, here's a patch that does it like that. I've verified that this builds on my netbsd/gxemul installation. regards, tom lane ------- =_aaaaaaaaaa0 Content-Type: text/x-diff; name="avoid-asm-set-mips2.patch"; charset="us-ascii" Content-ID: <3925.1560785347.2@sss.pgh.pa.us> Content-Description: avoid-asm-set-mips2.patch Content-Transfer-Encoding: quoted-printable diff --git a/configure b/configure index fd61bf6..57ef478 100755 --- a/configure +++ b/configure @@ -6900,6 +6900,57 @@ CXXFLAGS=3D"$CXXFLAGS $user_CXXFLAGS" BITCODE_CFLAGS=3D"$BITCODE_CFLAGS $user_BITCODE_CFLAGS" BITCODE_CXXFLAGS=3D"$BITCODE_CXXFLAGS $user_BITCODE_CXXFLAGS" = +case $host_cpu in + mips*) + # On MIPS, we must have ll/sc/sync instructions to do spinlocks, but = those + # do not exist in the long-obsolete MIPS-I architecture. Annoyingly,= many + # toolchains still default to emitting MIPS-I code, causing the assem= bler + # to reject these instructions. If using a gcc workalike, we can fix= this + # by adding -march=3Dmips2 to CFLAGS; otherwise, you're on your own t= o + # select the right compiler flag or use --disable-spinlocks. + if test "$enable_spinlocks" =3D yes -a x"$GCC" =3D x"yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether assembler= supports ll/sc/sync" >&5 +$as_echo_n "checking whether assembler supports ll/sc/sync... " >&6; } +if ${pgac_cv_have_mips_spinlock_insts+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +register volatile unsigned int *_l =3D NULL; + register int _res, _tmp; + __asm__ __volatile__( + " ll %0, %2 \n" + " sc %1, %2 \n" + " sync \n" + : "=3D&r" (_res), "=3D&r" (_tmp), "+R" (*_l) : : "memory"); + return _res; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + pgac_cv_have_mips_spinlock_insts=3Dyes +else + pgac_cv_have_mips_spinlock_insts=3Dno +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_have_mips_spinl= ock_insts" >&5 +$as_echo "$pgac_cv_have_mips_spinlock_insts" >&6; } + if test x"$pgac_cv_have_mips_spinlock_insts" =3D xno; then + CFLAGS=3D"$CFLAGS -march=3Dmips2" + CXXFLAGS=3D"$CXXFLAGS -march=3Dmips2" + BITCODE_CFLAGS=3D"$BITCODE_CFLAGS -march=3Dmips2" + BITCODE_CXXFLAGS=3D"$BITCODE_CXXFLAGS -march=3Dmips2" + fi + fi + ;; +esac + BITCODE_CFLAGS=3D$BITCODE_CFLAGS = BITCODE_CXXFLAGS=3D$BITCODE_CXXFLAGS diff --git a/configure.in b/configure.in index 4586a17..e1097aa 100644 --- a/configure.in +++ b/configure.in @@ -607,6 +607,38 @@ CXXFLAGS=3D"$CXXFLAGS $user_CXXFLAGS" BITCODE_CFLAGS=3D"$BITCODE_CFLAGS $user_BITCODE_CFLAGS" BITCODE_CXXFLAGS=3D"$BITCODE_CXXFLAGS $user_BITCODE_CXXFLAGS" = +case $host_cpu in + mips*) + # On MIPS, we must have ll/sc/sync instructions to do spinlocks, but = those + # do not exist in the long-obsolete MIPS-I architecture. Annoyingly,= many + # toolchains still default to emitting MIPS-I code, causing the assem= bler + # to reject these instructions. If using a gcc workalike, we can fix= this + # by adding -march=3Dmips2 to CFLAGS; otherwise, you're on your own t= o + # select the right compiler flag or use --disable-spinlocks. + if test "$enable_spinlocks" =3D yes -a x"$GCC" =3D x"yes"; then + AC_CACHE_CHECK([whether assembler supports ll/sc/sync], + [pgac_cv_have_mips_spinlock_insts], + [AC_COMPILE_IFELSE([AC_LANG_PROGRAM([], + [register volatile unsigned int *_l =3D NULL; + register int _res, _tmp; + __asm__ __volatile__( + " ll %0, %2 \n" + " sc %1, %2 \n" + " sync \n" + : "=3D&r" (_res), "=3D&r" (_tmp), "+R" (*_l) : : "memory"); + return _res;])], + [pgac_cv_have_mips_spinlock_insts=3Dyes], + [pgac_cv_have_mips_spinlock_insts=3Dno])]) + if test x"$pgac_cv_have_mips_spinlock_insts" =3D xno; then + CFLAGS=3D"$CFLAGS -march=3Dmips2" + CXXFLAGS=3D"$CXXFLAGS -march=3Dmips2" + BITCODE_CFLAGS=3D"$BITCODE_CFLAGS -march=3Dmips2" + BITCODE_CXXFLAGS=3D"$BITCODE_CXXFLAGS -march=3Dmips2" + fi + fi + ;; +esac + AC_SUBST(BITCODE_CFLAGS, $BITCODE_CFLAGS) AC_SUBST(BITCODE_CXXFLAGS, $BITCODE_CXXFLAGS) = diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index a9a92de..3af033b 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -614,7 +614,6 @@ tas(volatile slock_t *lock) = __asm__ __volatile__( " .set push \n" - " .set mips2 \n" " .set noreorder \n" " .set nomacro \n" " ll %0, %2 \n" @@ -636,7 +635,6 @@ do \ { \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips2 \n" \ " .set noreorder \n" \ " .set nomacro \n" \ " sync \n" \ ------- =_aaaaaaaaaa0--