From: Tom Lane <tgl@sss.pgh.pa.us>
To: Andres Freund <andres@anarazel.de>
cc: Dmitry Dolgov <9erthalion6@gmail.com>,
        Michael Paquier <michael.paquier@gmail.com>,
        Vincent Lachenal <vincent.lachenal@gmail.com>,
        PostgreSQL mailing lists <pgsql-bugs@postgresql.org>
Subject: Re: BUG #14897: Segfault on statitics SQL request
In-reply-to: <20171111181145.lo54au5awq3ib2nh@alap3.anarazel.de>
References: 
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 <17617.1510355215@sss.pgh.pa.us>
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 <CA+q6zcVE2FQ9irhENEy=2WjRWgV2hyzfYyOXFs36w=hsk4faBw@mail.gmail.com>
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 <CA+q6zcWwjTNgA6JiqQ5L-oAFF5X9ONtKSAvznte63A7Zb7zaww@mail.gmail.com>
 <20171111171620.td6vtnmijcloj6k5@alap3.anarazel.de>
 <3914.1510422100@sss.pgh.pa.us>
 <20171111174512.ikd3zrx2i5ssxpww@alap3.anarazel.de>
 <4612.1510422869@sss.pgh.pa.us>
 <20171111181145.lo54au5awq3ib2nh@alap3.anarazel.de>
Comments: In-reply-to Andres Freund <andres@anarazel.de>
	message dated "Sat, 11 Nov 2017 10:11:45 -0800"
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Date: Sat, 11 Nov 2017 14:31:47 -0500
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Andres Freund <andres@anarazel.de> writes:
> On 2017-11-11 12:54:29 -0500, Tom Lane wrote:
>> I think that would be better served by a flag like
>> MCXT_ALLOC_ALIGN_CACHELINE than by having the callers demand a
>> specific numeric alignment value --- it'd be a lot easier to make the
>> alignment match actual hardware requirements if it were being inserted
>> at one specific place.

> Specifying MCXT_ALLOC_ALIGN_CACHELINE rather than CACHELINE_ALIGNMENT
> doesn't seem to make it meaningfully harder to adjust. Or are you
> thinking of probing the hardware?

Yeah, the latter.  The two approaches seem pretty much equivalent if
you're assuming compile-time decisions, but if we ever wanted a run-
time decision, I think having a flag bit that's interpreted inside
MemoryContextAllocExtended would be easier to deal with.

			regards, tom lane


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