Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhNDy-00042B-Ch for pgsql-hackers@arkaria.postgresql.org; Sat, 06 Jun 2020 01:02:14 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.92) (envelope-from ) id 1jhNDv-0001yM-V0 for pgsql-hackers@arkaria.postgresql.org; Sat, 06 Jun 2020 01:02:11 +0000 Received: from magus.postgresql.org ([2a02:c0:301:0:ffff::29]) by malur.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhNDv-0001xz-Nn for pgsql-hackers@lists.postgresql.org; Sat, 06 Jun 2020 01:02:11 +0000 Received: from sss.pgh.pa.us ([66.207.139.130]) by magus.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhNDn-0000Dp-2w for pgsql-hackers@lists.postgresql.org; Sat, 06 Jun 2020 01:02:11 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.15.2/8.15.2) with ESMTP id 05611u5N1642805; Fri, 5 Jun 2020 21:01:56 -0400 From: Tom Lane To: Andres Freund cc: Robert Haas , pgsql-hackers@lists.postgresql.org Subject: Re: Atomic operations within spinlocks In-reply-to: <20200606001926.zin5getvvhqppnm2@alap3.anarazel.de> References: <1141819.1591208385@sss.pgh.pa.us> <20200603204542.reuladbmgmjqzoi6@alap3.anarazel.de> <1253593.1591293439@sss.pgh.pa.us> <20200604185525.wuyjtkluppj4eddr@alap3.anarazel.de> <1256701.1591297654@sss.pgh.pa.us> <20200605023302.g6v3ydozy5txifji@alap3.anarazel.de> <20200606001926.zin5getvvhqppnm2@alap3.anarazel.de> Comments: In-reply-to Andres Freund message dated "Fri, 05 Jun 2020 17:19:26 -0700" MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-ID: <1642803.1591405316.1@sss.pgh.pa.us> Date: Fri, 05 Jun 2020 21:01:56 -0400 Message-ID: <1642804.1591405316@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Precedence: bulk Andres Freund writes: > I wrote a patch for this, and when I got around to to testing it, I > found that our tests currently don't pass when using both > --disable-spinlocks and --disable-atomics. Turns out to not be related > to the issue above, but the global barrier support added in 13. > That *reads* two 64 bit atomics in a signal handler. Which is normally > fine, but not at all cool when atomics (or just 64 bit atomics) are > backed by spinlocks. Because we can "self interrupt" while already > holding the spinlock. This is the sort of weird platform-specific problem that I'd prefer to avoid by minimizing our expectations of what spinlocks can be used for. > I'm not really sure what to do about that issue. The easisest thing > would probably be to change the barrier generation to 32bit (which > doesn't have to use locks for reads in any situation). Yeah, I think we need a hard rule that you can't use a spinlock in an interrupt handler --- which means no atomics that don't have non-spinlock implementations on every platform. At some point I think we'll have to give up --disable-spinlocks; it's really of pretty marginal use (how often does anyone port PG to a new CPU type?) and the number of weird interactions it adds in this area seems like more than it's worth. But of course requiring 64-bit atomics is still a step too far. > Randomly noticed while looking at the code: > uint64 flagbit = UINT64CONST(1) << (uint64) type; I'm surprised we didn't get any compiler warnings about that. regards, tom lane