Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhOx6-0007QA-K9 for pgsql-hackers@arkaria.postgresql.org; Sat, 06 Jun 2020 02:52:56 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.92) (envelope-from ) id 1jhOx5-0002ZW-Cq for pgsql-hackers@arkaria.postgresql.org; Sat, 06 Jun 2020 02:52:55 +0000 Received: from makus.postgresql.org ([2001:4800:3e1:1::229]) by malur.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhOx5-0002ZP-5o for pgsql-hackers@lists.postgresql.org; Sat, 06 Jun 2020 02:52:55 +0000 Received: from sss.pgh.pa.us ([66.207.139.130]) by makus.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jhOx1-0002sE-HY for pgsql-hackers@lists.postgresql.org; Sat, 06 Jun 2020 02:52:54 +0000 Received: from sss1.sss.pgh.pa.us (localhost [127.0.0.1]) by sss.pgh.pa.us (8.15.2/8.15.2) with ESMTP id 0562qlsA1647174; Fri, 5 Jun 2020 22:52:47 -0400 From: Tom Lane To: Andres Freund cc: Robert Haas , pgsql-hackers@lists.postgresql.org Subject: Re: Atomic operations within spinlocks In-reply-to: <20200606023103.avzrctgv7476xj7i@alap3.anarazel.de> References: <1141819.1591208385@sss.pgh.pa.us> <20200603204542.reuladbmgmjqzoi6@alap3.anarazel.de> <1253593.1591293439@sss.pgh.pa.us> <20200604185525.wuyjtkluppj4eddr@alap3.anarazel.de> <1256701.1591297654@sss.pgh.pa.us> <20200605023302.g6v3ydozy5txifji@alap3.anarazel.de> <20200606001926.zin5getvvhqppnm2@alap3.anarazel.de> <1642804.1591405316@sss.pgh.pa.us> <20200606023103.avzrctgv7476xj7i@alap3.anarazel.de> Comments: In-reply-to Andres Freund message dated "Fri, 05 Jun 2020 19:31:03 -0700" MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-ID: <1647172.1591411967.1@sss.pgh.pa.us> Date: Fri, 05 Jun 2020 22:52:47 -0400 Message-ID: <1647173.1591411967@sss.pgh.pa.us> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Precedence: bulk Andres Freund writes: > On 2020-06-05 21:01:56 -0400, Tom Lane wrote: >> At some point I think we'll have to give up --disable-spinlocks; it's >> really of pretty marginal use (how often does anyone port PG to a new >> CPU type?) and the number of weird interactions it adds in this area >> seems like more than it's worth. > Indeed. And any new architecture one would port PG to would have good > enough compiler intrinsics to make that trivial. I still think it'd make > sense to have a fallback implementation using compiler intrinsics... > And I think we should just require 32bit atomics at the same time. Would > probably kill gaur though. Not only gaur. A quick buildfarm survey finds these active members reporting not having 32-bit atomics: anole | 2020-06-05 11:20:17 | pgac_cv_gcc_atomic_int32_cas=no chipmunk | 2020-05-29 22:27:56 | pgac_cv_gcc_atomic_int32_cas=no curculio | 2020-06-05 22:30:06 | pgac_cv_gcc_atomic_int32_cas=no frogfish | 2020-05-31 13:00:25 | pgac_cv_gcc_atomic_int32_cas=no gaur | 2020-05-19 13:33:25 | pgac_cv_gcc_atomic_int32_cas=no gharial | 2020-06-05 12:41:14 | pgac_cv_gcc_atomic_int32_cas=no hornet | 2020-06-05 09:11:26 | pgac_cv_gcc_atomic_int32_cas=no hoverfly | 2020-06-05 22:06:14 | pgac_cv_gcc_atomic_int32_cas=no locust | 2020-06-05 10:14:29 | pgac_cv_gcc_atomic_int32_cas=no mandrill | 2020-06-05 09:20:03 | pgac_cv_gcc_atomic_int32_cas=no prairiedog | 2020-06-05 09:55:49 | pgac_cv_gcc_atomic_int32_cas=no It looks to me like this is mostly about compiler support not the hardware; that doesn't make it not a problem, though. (I also remain skeptical about the quality of the compiler intrinsics on non-mainstream hardware.) regards, tom lane