Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1orNxI-0007X0-JZ for pgsql-hackers@arkaria.postgresql.org; Sat, 05 Nov 2022 18:31:44 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.92) (envelope-from ) id 1orNxH-0004PQ-Fc for pgsql-hackers@arkaria.postgresql.org; Sat, 05 Nov 2022 18:31:43 +0000 Received: from makus.postgresql.org ([2001:4800:3e1:1::229]) by malur.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1orNxH-0004P3-1A for pgsql-hackers@lists.postgresql.org; Sat, 05 Nov 2022 18:31:43 +0000 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]) by makus.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1orNxE-0006MV-FC for pgsql-hackers@lists.postgresql.org; Sat, 05 Nov 2022 18:31:41 +0000 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id C05BC3200495; Sat, 5 Nov 2022 14:31:38 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sat, 05 Nov 2022 14:31:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anarazel.de; h= cc:cc:content-type:date:date:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to; s=fm3; t=1667673098; x=1667759498; bh=aCwQnv7IMe GesWfkjZzS38Atr0lD42Xs7LpODpDwTbw=; b=e44N7jGO+k76KgDygWhAlOSVp6 nIVWvY77UD+pEPZ7frn2gtZrcAz8ELBVSb3wXWesCUiBINPNnavMVqQbByzcMGRk JfhYgBKXxpf84/Cd9rdtx+YZNMFk6Zn55LzUjMrfxY601RhIWReuhtKxOt9uYO3p udKcaPGt6S10GvSMo2XqBCsPyXmSsGV7AoGYbN6E1+1abQr7Ncruuj+Nlx1Y0CIs QPKJhaEFbssCNUMfbDXJbeaih8ZsNFlwvljM9c58LVT9VHAyw9mYjkePxRiszXiH s9oEjf0K7LTYdL/CJqeDD1eA4zRhMU9v5JGFjCJbHf2RldH9CcFJQ+sRU3gg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-type:date:date:feedback-id :feedback-id:from:from:in-reply-to:in-reply-to:message-id :mime-version:references:reply-to:sender:subject:subject:to:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; t=1667673098; x=1667759498; bh=aCwQnv7IMeGesWfkjZzS38Atr0lD 42Xs7LpODpDwTbw=; b=H6vEe4PcdbyTf92vvjASDkGkc4gdyGnmEQ5G7wlwxbZn xzoYNgEZljKk4RA2XKtzmOoCf4PzbKbYUMazGe7lb8HuTiOfVfV68UMeE1NfE4PM 6gHPK9ER0ICUu/7HZF3iUrUDpTz4tuoxlBgQ5FUzRfJlLce6OmmIs0D226VGNQHh jK2loQO3DP8m05j7Zr2qwQ+R0BiPhD/DcmJICTGao/0kcAhqHRiPEyqSsZE6oVCS d5faiLTvvZHIJJZ1999ipUtW3198r7I2C22qAytMZ9mt/Yi5a2gqrw65DDflH4uA 4aL3k1aI3NJIzF8b84W473Nyettc2JD9YKTsUCN4aA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrvdefgdduuddtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepfffhvfevuffkfhggtggujgesthdtredttddtvdenucfhrhhomheptehnughr vghsucfhrhgvuhhnugcuoegrnhgurhgvshesrghnrghrrgiivghlrdguvgeqnecuggftrf grthhtvghrnhepffduvdefieduueduhefhgfetkeefteelvefffeetffeuhfdtjeetudek vdfhudelnecuffhomhgrihhnpegrrhhmrdgtohhmnecuvehluhhsthgvrhfuihiivgeptd enucfrrghrrghmpehmrghilhhfrhhomheprghnughrvghssegrnhgrrhgriigvlhdruggv X-ME-Proxy: Feedback-ID: id4a34324:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 5 Nov 2022 14:31:37 -0400 (EDT) Date: Sat, 5 Nov 2022 11:31:36 -0700 From: Andres Freund To: Niyas Sait Cc: Ian Lawrence Barwick , Michael Paquier , Tom Lane , Thomas Munro , Julien Rouhaud , PostgreSQL Hackers Subject: Re: [PATCH] Add native windows on arm64 support Message-ID: <20221105183136.hfxyl5dclxdcoyih@awork3.anarazel.de> References: <3886822.1661905738@sss.pgh.pa.us> <20476.1661967233@sss.pgh.pa.us> <271611.1661998926@sss.pgh.pa.us> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk Hi, On 2022-11-03 11:06:46 +0000, Niyas Sait wrote: > I've attached a new version of the patch which excludes the already merged > ASLR changes and add > small changes to handle latest changes in the build scripts. Note that we're planning to remove the custom windows build scripts before the next release, relying on the meson build instead. > diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h > index 8b19ab160f..bf6a6dba35 100644 > --- a/src/include/storage/s_lock.h > +++ b/src/include/storage/s_lock.h > @@ -708,13 +708,21 @@ typedef LONG slock_t; > #define SPIN_DELAY() spin_delay() > > /* If using Visual C++ on Win64, inline assembly is unavailable. > - * Use a _mm_pause intrinsic instead of rep nop. > + * Use _mm_pause (x64) or __isb(arm64) intrinsic instead of rep nop. > */ > #if defined(_WIN64) > static __forceinline void > spin_delay(void) > { > +#ifdef _M_ARM64 > + /* > + * arm64 way of hinting processor for spin loops optimisations > + * ref: https://community.arm.com/support-forums/f/infrastructure-solutions-forum/48654/ssetoneon-faq > + */ > + __isb(_ARM64_BARRIER_SY); > +#else > _mm_pause(); > +#endif > } > #else > static __forceinline void I think we should just apply this, there seems very little risk of making anything worse, given the gating to _WIN64 && _M_ARM64. > diff --git a/src/port/pg_crc32c_armv8.c b/src/port/pg_crc32c_armv8.c > index 9e301f96f6..981718752f 100644 > --- a/src/port/pg_crc32c_armv8.c > +++ b/src/port/pg_crc32c_armv8.c > @@ -14,7 +14,9 @@ > */ > #include "c.h" > > +#ifndef _MSC_VER > #include > +#endif > > #include "port/pg_crc32c.h" This won't suffice with the meson build, since the relevant configure test also uses arm_acle.h: elif host_cpu == 'arm' or host_cpu == 'aarch64' prog = ''' #include int main(void) { unsigned int crc = 0; crc = __crc32cb(crc, 0); crc = __crc32ch(crc, 0); crc = __crc32cw(crc, 0); crc = __crc32cd(crc, 0); /* return computed value, to prevent the above being optimized away */ return crc == 0; } ''' if cc.links(prog, name: '__crc32cb, __crc32ch, __crc32cw, and __crc32cd without -march=armv8-a+crc', args: test_c_args) # Use ARM CRC Extension unconditionally cdata.set('USE_ARMV8_CRC32C', 1) have_optimized_crc = true elif cc.links(prog, name: '__crc32cb, __crc32ch, __crc32cw, and __crc32cd with -march=armv8-a+crc', args: test_c_args + ['-march=armv8-a+crc']) # Use ARM CRC Extension, with runtime check cflags_crc += '-march=armv8-a+crc' cdata.set('USE_ARMV8_CRC32C', false) cdata.set('USE_ARMV8_CRC32C_WITH_RUNTIME_CHECK', 1) have_optimized_crc = true endif endif The meson checking logic is used both for msvc and other compilers, so this will need to work with both. > diff --git a/src/tools/msvc/gendef.pl b/src/tools/msvc/gendef.pl > index d6bed1ce15..f1e0ff446b 100644 > --- a/src/tools/msvc/gendef.pl > +++ b/src/tools/msvc/gendef.pl > @@ -120,9 +120,9 @@ sub writedef > { > my $isdata = $def->{$f} eq 'data'; > > - # Strip the leading underscore for win32, but not x64 > + # Strip the leading underscore for win32, but not x64 and arm64 > $f =~ s/^_// > - unless ($arch eq "x86_64"); > + unless ($arch ne "x86"); > > # Emit just the name if it's a function symbol, or emit the name > # decorated with the DATA option for variables. > @@ -143,7 +143,7 @@ sub writedef > sub usage > { > die("Usage: gendef.pl --arch --deffile --tempdir files-or-directories\n" > - . " arch: x86 | x86_64\n" > + . " arch: x86 | x86_64 | arm64 \n" > . " deffile: path of the generated file\n" > . " tempdir: directory for temporary files\n" > . " files or directories: object files or directory containing object files\n" > @@ -160,7 +160,7 @@ GetOptions( > 'tempdir:s' => \$tempdir,) or usage(); > > usage("arch: $arch") > - unless ($arch eq 'x86' || $arch eq 'x86_64'); > + unless ($arch eq 'x86' || $arch eq 'x86_64' || $arch eq 'arm64'); > > my @files; > Seems reasonable. Greetings, Andres Freund