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[162.195.168.172]) by smtp.gmail.com with ESMTPSA id l21-20020a05663814d500b0047ecdd772f4sm486094jak.52.2024.03.28.14.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 14:51:37 -0700 (PDT) Date: Thu, 28 Mar 2024 16:51:36 -0500 From: Nathan Bossart To: "Amonson, Paul D" Cc: Tom Lane , David Rowley , Andres Freund , Alvaro Herrera , "Shankaran, Akash" , Noah Misch , Matthias van de Meent , "pgsql-hackers@lists.postgresql.org" Subject: Re: Popcount optimization using AVX512 Message-ID: <20240328215136.GA918358@nathanxps13> References: <2490633.1711379522@sss.pgh.pa.us> <20240325200551.GB2924132@nathanxps13> <20240327220010.GA231058@nathanxps13> <20240328213854.GA916732@nathanxps13> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240328213854.GA916732@nathanxps13> List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk On Thu, Mar 28, 2024 at 04:38:54PM -0500, Nathan Bossart wrote: > Here is a v14 of the patch that I think is beginning to approach something > committable. Besides general review and testing, there are two things that > I'd like to bring up: > > * The latest patch set from Paul Amonson appeared to support MSVC in the > meson build, but not the autoconf one. I don't have much expertise here, > so the v14 patch doesn't have any autoconf/meson support for MSVC, which > I thought might be okay for now. IIUC we assume that 64-bit/MSVC builds > can always compile the x86_64 popcount code, but I don't know whether > that's safe for AVX512. > > * I think we need to verify there isn't a huge performance regression for > smaller arrays. IIUC those will still require an AVX512 instruction or > two as well as a function call, which might add some noticeable overhead. I forgot to mention that I also want to understand whether we can actually assume availability of XGETBV when CPUID says we support AVX512: > + /* > + * We also need to check that the OS has enabled support for the ZMM > + * registers. > + */ > +#ifdef _MSC_VER > + return (_xgetbv(0) & 0xe0) != 0; > +#else > + uint64 xcr = 0; > + uint32 high; > + uint32 low; > + > +__asm__ __volatile__(" xgetbv\n":"=a"(low), "=d"(high):"c"(xcr)); > + return (low & 0xe0) != 0; > +#endif -- Nathan Bossart Amazon Web Services: https://aws.amazon.com