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From: Greg Burd <[email protected]>
To: Andres Freund <[email protected]>
Cc: PostgreSQL Hackers <[email protected]>
Cc: Dave Cramer <[email protected]>
Subject: Re: [PATCH] Fix ARM64/MSVC atomic memory ordering issues on Win11 by adding explicit DMB ​barriers
Date: Fri, 21 Nov 2025 14:37:08 -0500
Message-ID: <[email protected]> (raw)
In-Reply-To: <ij5efu2ul2keqyf5uzjjubb424kuxttgtrtceiuajjnpd3sts3@s4g2z5t3wp5z>
References: <ij5efu2ul2keqyf5uzjjubb424kuxttgtrtceiuajjnpd3sts3@s4g2z5t3wp5z>


On Nov 20 2025, at 7:07 pm, Andres Freund <[email protected]> wrote:

> Hi,
> 
> On 2025-11-20 19:03:47 -0500, Andres Freund wrote:
>> > MSVC's _InterlockedCompareExchange() intrinsic on ARM64 performs the
>> > atomic operation but does NOT emit the necessary Data Memory Barrier
>> > (DMB) instructions [4][5].
>> 
>> I couldn't reproduce this result when playing around on godbolt. By specifying
>> /arch:armv9.4 msvc can be convinced to emit the code for the
>> intrinsics inline
>> (at least for most of them).  And that makes it visible that
>> _InterlockedCompareExchange() results in a "casal" instruction.
>> Looking that
>> up shows:
>>   https://developer.arm.com/documentation/dui0801/l/A64-Data-Transfer-Instructions/CASA--CASAL--CAS--C...-
>> which includes these two statements:
>> "CASA and CASAL load from memory with acquire semantics."
>> "CASL and CASAL store to memory with release semantics."
> 
> Further evidence for that is that
> https://learn.microsoft.com/en-us/windows/win32/api/winnt/nf-winnt-interlockedcompareexchange
> states:
> "This function generates a full memory barrier (or fence) to ensure
> that memory operations are completed in order."
> 
> (note that we are using the function, not the intrinsic for TAS())

Got it, thanks.

> Greetings,
> 
> Andres

best.

-greg

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