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Wed, 14 Aug 2024 10:46:38 +0300 (EEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iki.fi; s=lahtoruutu; t=1723621601; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m/E8BbTQ1H1015S1r0LV6gZmDtegIKY+ysWzKvHWr5k=; b=dsmtVShhAoTVro3c7xyVmaaAEj/K4gtuXgpfkh7kNBEjFE1acj68I4sXhbzNtQmqJOCfSp oC/NQk5/jTrxtHP7qqnkC3WweaywoPqhdi6yL/Qu6/cmZr1nER7zZSosWOag9dMCh5yoMy DS2X8zuGKsbJA8cE8v3DfrFNpeNoLB+Gz7LNemTRFELuijvNO9RawtWNAEssSVFrRmFyJg O6G7lNT6vzKDXcfO/98aX65WAMWa2ykQxt8+TOhQRNlRa724+DK6Pz2UFsuvoMrj/Mt/uv mHV6V9dmwilhm8IQ/GQA8bWe9gddU7+RrXoBiGlZGerN1QYi5dEetKdxkeFUHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=iki.fi; s=lahtoruutu; t=1723621601; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m/E8BbTQ1H1015S1r0LV6gZmDtegIKY+ysWzKvHWr5k=; b=vaRHcfOAAITTkAF8ACgP6kV95BeWjcQJyXb68NVpOTBRfZlIXUo39/M9dAVRmaOqLLJRYj GGNQxzBoJd9GP8V3pQuDur+hMWPSYGVSnEI6mUxqdwsyIn8uNHn4wWhKYwO6HHZ3AAui3Z H0HxAtj4eGDHlcFHw335H/t/CxMsYYg5z0ajVmX14rNlmb7GEASJdtfdH6Y3cvvzhY2v0d Qj+A2TBK8bzGKfSf7qLtPY/Tlb5ERkOhGu4fm59lNi4g8Rajii55CE6SwB9bSHcVNsIJmi xDKr+UQTrsDT4mZD9AnwvKXtgff9+npC1hktB8o7CwPZSLML8aP54Q0llHDXeQ== ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=hlinnaka smtp.mailfrom=hlinnaka@iki.fi ARC-Seal: i=1; s=lahtoruutu; d=iki.fi; t=1723621601; a=rsa-sha256; cv=none; b=XuOAW7J3OaWOroOGpACBkwdIxKhQeyDn5H6n8j2/nyRIcLeN6MdbBpoZWfsLvU1WIlPUaJ 3V1ncN9RoSMB/Hd07HAJhMMLVfWPkPqiXFXgrcpxLy0/tzs75YMErJBXhaH1DbYvrCRb1q /2br6yGnC6DyDdgShckGr8zVTWPSHAiEzm/wEFOuA9+X9AQC/YDuoS/o0o38s8LztMNCkx qpg2DE0hu078eZ6rxTz/pX1sooZvLyNwfIzdREomxpRWVsyUArhzS0wFBtSbByvQ1LXRjz 8ePt3FB1gnouOAz6O/OGMZrTccEVoDA+xMv9XEsHPsTtXUP+smZbA/76SIxCPw== Message-ID: <95a44be0-b2f8-464a-8984-771d892b1cac@iki.fi> Date: Wed, 14 Aug 2024 10:46:38 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: AIX support To: Srirama Kucherlapati , Heikki Linnakangas , Laurenz Albe , Bruce Momjian Cc: Peter Eisentraut , Alvaro Herrera , "pgsql-hackers@postgresql.org" , Noah Misch , Michael Paquier , Andres Freund , Tom Lane , Thomas Munro , "tvk1271@gmail.com" , "postgres-ibm-aix@wwpdl.vnet.ibm.com" References: <698dd3efec644b5c0dd6220d73033f8153ae2fde.camel@cybertec.at> Content-Language: en-US From: Heikki Linnakangas In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk On 14/08/2024 06:31, Srirama Kucherlapati wrote: > Hi Heikki & Team, > > I tried to look at the assembly code changes with our team, in the below > file. > > diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h > index 29ac6cdcd9..69582f4ae7 100644 > --- a/src/include/storage/s_lock.h > +++ b/src/include/storage/s_lock.h > static __inline__ int > tas(volatile slock_t *lock) > @@ -424,17 +430,15 @@ tas(volatile slock_t *lock) > __asm__ __volatile__( > "        lwarx   %0,0,%3,1        \n" > "        cmpwi   %0,0                \n" > "        bne     $+16                \n"                /* branch to li > %1,1 */ > "        addi    %0,%0,1                \n" > "        stwcx.  %0,0,%3                \n" > "        beq     $+12                \n"                /* branch to > lwsync */ > "        li      %1,1                \n" > "        b       $+12                \n"                /* branch to end > of asm sequence */ > "        lwsync                                \n" > "        li      %1,0                \n" > :        "=&b"(_t), "=r"(_res), "+m"(*lock) > :        "r"(lock) > :        "memory", "cc"); > > For the changes in the above file,  this code is very specific to power > architecture we need to use the IBM Power specific asm code only, rather > than using the GNU assembler. Also, all these asm specific code is under > the macro __ppc__, which should not impact any other platforms. I see > there is a GCC specific implementation (under this macro #if > defined(HAVE_GCC__SYNC_INT32_TAS)) in the same file as well. I'm sorry, I don't understand what you're saying here. Do you mean that we don't need to do anything here, and the code we have in s_lock.h in 'master' now will work fine on AIX? Or do we need to (re-)do some changes to support AIX again? If we only support GCC, can we use the __sync_lock_test_and_set() builtin instead? If any changes are required, please include them in the patch. That'll make it clear what exactly you're proposing. > +#define TAS(lock)                      _check_lock((slock_t *) (lock), > 0, 1) > > +#define S_UNLOCK(lock)         _clear_lock((slock_t *) (lock), 0) > > The above changes are specific to AIX kernel and it operates on fixed > kernel memory. This is more like a compare_and_swap functionality with > sync capability. For all the assemble code I think it would be better to > use the IBM Power specific asm code to gain additional performance. You mean we don't need the above? Ok, good. > I was trying to understand here wrt to both the assemble changes if you > are looking for anything specific to the architecture. I don't know. You tell me what makes most sense on AIX / powerpc. > Attached is the patch for the previous comments, kindly please let me > know your comments. Is this all that's needed to resurrect AIX support? -- Heikki Linnakangas Neon (https://neon.tech)