Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1quLEz-0004rm-6e for pgsql-hackers@arkaria.postgresql.org; Sat, 21 Oct 2023 23:18:45 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.94.2) (envelope-from ) id 1quLDx-008Teu-LV for pgsql-hackers@arkaria.postgresql.org; Sat, 21 Oct 2023 23:17:42 +0000 Received: from magus.postgresql.org ([2a02:c0:301:0:ffff::29]) by malur.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1quLDx-008Tb9-86 for pgsql-hackers@lists.postgresql.org; Sat, 21 Oct 2023 23:17:42 +0000 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by magus.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94.2) (envelope-from ) id 1quLDq-001yWY-Ot for pgsql-hackers@lists.postgresql.org; Sat, 21 Oct 2023 23:17:41 +0000 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9a58dbd5daeso310389266b.2 for ; Sat, 21 Oct 2023 16:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697930252; x=1698535052; darn=lists.postgresql.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=hD2+GbL6xDH0lN3qdX7jbmLyxBZ8HGuH3ZbXvXnDxs8=; b=LbvZL75tKIkWfUfv/Mnx6GVFuvBDF3ZI+sPL74KlEqOoNe+haLt4YXWrTx5xEzaxEN s6fCsY/kPEnMAsb2E1kaFvlMbWGxjAWXLfLFR20mnsosys4wFcfVdl/r2+fnGIdb3mnX hAd/1A7h0V4gmbtl2mQqWDF30wH755p6dGIBtIR6AzNkY0mhgmxmJFWo5+k2V+7ocRll dSMPHqGf3L4gdkImQmc3nnmxmZdo6SVZ+M5LJsc9FBqc2g3RA/t/Xel39vSldy1FfXtd cuwcEeQPPmuuuVg861ZtiR9Q6fl/V9nSXzCOu64XRPS8tUGPHxHUBxlqdra1sYatLVI0 nz4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697930252; x=1698535052; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hD2+GbL6xDH0lN3qdX7jbmLyxBZ8HGuH3ZbXvXnDxs8=; b=Lwqf2dd6nwUyIQ5SdoQBlptCsJlTMzpfwrpXCheWfzNd5PSlAf7fXSjkuBnaUK2wDH OmDgFK98m5kFEMrHDuQtNMcuvu1JxF9Szbl2ELu5533P4EMYeOTSGGPLe9PIlkNtUBig eEIgUDxTQPin36CAJZI0IdlsZq5N4bKF21/u4EAXjeIibKp0+MPQ0pmff/6NNcAIoIA4 nGyiYPXiteqw4lSWRlOASwzyA263HCDWqkClONSQihjboC1EN59lu4aV1qUo0u4murqR LZ1Vgb09zbN5zR2x5h/pmBZhZNkaYp8T7tf2eOpITJwqaEJdnAPN1Qg9Zuge+Ay5nObU 49VA== X-Gm-Message-State: AOJu0YxycQnmztIPQGUUGopkQoGoYFD0lsJ8j4+zaNKM22+erHL+UhKE MrqIlhZ8vst3aQbmDJuYT+v6vyfGxqrJyUBMBSs= X-Google-Smtp-Source: AGHT+IEwhgfxZfl3rRpKqQ5hqb/H3rdkDhaFcXZZ4tKpy6DvUKARO1i926HYvW9CIoTgp8yCrDbmRRacYC+GgIu5Fhg= X-Received: by 2002:a17:906:db09:b0:9be:c2cd:aa29 with SMTP id xj9-20020a170906db0900b009bec2cdaa29mr3474502ejb.77.1697930252188; Sat, 21 Oct 2023 16:17:32 -0700 (PDT) MIME-Version: 1.0 References: <5716086.DvuYhMxLoT@aivenlaptop> <2700884.mvXUDI8C0e@aivenlaptop> <20231021060805.of3ukvyfmxnlvwcd@awork3.anarazel.de> In-Reply-To: <20231021060805.of3ukvyfmxnlvwcd@awork3.anarazel.de> From: Thomas Munro Date: Sun, 22 Oct 2023 12:16:54 +1300 Message-ID: Subject: Re: LLVM 16 (opaque pointers) To: Andres Freund Cc: Ronan Dunklau , =?UTF-8?B?RGV2cmltIEfDvG5kw7x6?= , PostgreSQL Hackers , Fabien COELHO , Dmitry Dolgov <9erthalion6@gmail.com>, Tom Stellard , Mark Wong Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk On Sat, Oct 21, 2023 at 7:08=E2=80=AFPM Andres Freund = wrote: > I've attached a patch revision that I spent the last couple hours working > on. It's very very roughly based on a patch Tom Stellard had written (whi= ch I > think a few rpm packages use). But instead of encoding details about spec= ific > layout details, I made the code check if the data layout works and fall b= ack > to the cpu / features used for llvmjit_types.bc. This way it's not s390x > specific, future odd architecture behaviour would "automatically" be hand= led > the same The explanation makes sense and this seems like a solid plan to deal with it. I didn't try on a s390x, but I tested locally on our master branch with LLVM 7, 10, 17, 18, and then I hacked your patch to take the fallback path as if a layout mismatch had been detected, and it worked fine: 2023-10-22 11:49:55.663 NZDT [12000] DEBUG: detected CPU "skylake", with features "...", resulting in layout "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 2023-10-22 11:49:55.664 NZDT [12000] DEBUG: detected CPU / features yield incompatible data layout, using values from module instead 2023-10-22 11:49:55.664 NZDT [12000] DETAIL: module CPU "x86-64", features "...", resulting in layout "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + To deal with that, check if data layouts match during JIT initialization. If + the runtime detected cpu / features result in a different layout, try if the + cpu/features recorded in in llvmjit_types.bc work. s|try |check | s| in in | in | + errmsg_internal("could not determine working CPU / feature comination for JIT compilation"), s|comination|combination| s| / |/|g