On Mon, 30 Mar 2026 at 15:01, John Naylor <johncnaylorls@gmail.com> wrote:
> I don't remember the last time anyone did measurements, so I went
> ahead and did that:
>
> master: 945ms
> 32 AVX2: 335ms
> 64 AVX2: 220ms

I'm guessing this is on a recent Intel. Any extra width is helpful on Intel as they doubled vpmulld latency from under us after we had settled on this algorithm. uops.info shows that the most recent Arrow Lake-P cores bring the latency down to 5. B Intels product lineup is so confusing that it's hard to tell which products this core ships in. As far as I can tell not in any Xeons yet. AMD has had 3 cycle vpmulld since Zen 3.

Out of curiosity I tried some approximate numbers on Zen 5 for differing N_SUMS values. Numbers are ns per iteration for 10M iterations.

GCC 15.2 -O3: