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boundary="_000_DS0PR15MB5623ECC0499C5087EFD729EADB652DS0PR15MB5623namp_" MIME-Version: 1.0 X-OriginatorOrg: in.ibm.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DS0PR15MB5623.namprd15.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 30f2642a-ec84-4f09-050a-08dcd3ea286b X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Sep 2024 11:49:43.3251 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: fcf67057-50c9-4ad4-98f3-ffca64add9e9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2fiWOqtYnDRFQ1yo3R2xNZUtWda7nuDaxwK7LBYnHS8X75Sgs4OEs+Ar9qjleaYmUciN+XTvOwwVf/aKyvPP+g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR15MB6448 X-Proofpoint-GUID: X8rNstfA7Ofq7Cjb2TRLw7P6M1Glutxw X-Proofpoint-ORIG-GUID: 8poZvjeBu_Xlqs2cBrjn5a4v12avnMxk Subject: RE: AIX support X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-13_09,2024-09-13_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 mlxlogscore=979 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409130080 List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk --_000_DS0PR15MB5623ECC0499C5087EFD729EADB652DS0PR15MB5623namp_ Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable > The PPC asm code was originally written in 2002, and the first use of > _ sync_lock_test_and_set(), for ARM, appeared in 2012. The commit tha= t > made __sync_lock_test_and_set() be chosen automatically for platforms > that don't specify anything else was added in 2022. Thanks for the info. ------------------ > Ok, if we don't need the assembler code at all, that's good. A patch = to > introduce AIX support should not change it for non-AIX powerpc system= s > though. That might be a good change, but would need to be justified > separately, e.g. by some performance testing, and should be a separa= te > patch. > If you make no changes to s_lock.h at all, will it work? Why not? With the existing asm code I see there are some syntax errors, being hit. But after reverting the old changes the issues resolved. Below are diffs. static __inline__ int tas(volatile slock_t *lock) { @@ -424,17 +413,15 @@ tas(volatile slock_t *lock) __asm__ __volatile__( " lwarx %0,0,%3,1 \n" " cmpwi %0,0 \n" -" bne 1f \n" +" bne $+16 \n" /* branch to li %1,1 */ " addi %0,%0,1 \n" " stwcx. %0,0,%3 \n" -" beq 2f \n" -"1: \n" +" beq $+12 \n" /* branch to lwsync */ " li %1,1 \n" -" b 3f \n" -"2: \n" +" b $+12 \n" /* branch to end of asm= sequence */ " lwsync \n" " li %1,0 \n" -"3: \n" + : "=3D&b"(_t), "=3Dr"(_res), "+m"(*lock) : "r"(lock) : "memory", "cc"); Let me know if I need to run any perf tools to check the performance of the __sync_lock_test_and_set change. --------------- > > I mean this part of the code is needed as this is specific to AIX k= ernel memory > > operation which is different from __sync_lock_test_and_set(). > > > > I would like to mention that the changes made in src/include/storag= e/s_lock.h > > are pretty much required and need to be operated in assemble specif= ic to IBM > > Power architecture. > Was that earlier statement incorrect? Is the manual wrong or outdated= or > not applicable to us? Here this change is specific to AIX, but since we are compiling with gcc, t= his is not applicable. But I will try with __sync* routines and check. --------------- > Do you still need mkldexport.sh? Surely there's a better way to do th= at > in year 2024. Some quick googling says there's a '-bexpall' option to > 'ld', which kind of sounds like what we want. Will that work? How do > other programs do this? Thanks for looking into this, I=92m working on this, I will let you know. Thanks, Sriram. --_000_DS0PR15MB5623ECC0499C5087EFD729EADB652DS0PR15MB5623namp_ Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable


    > The PPC asm code was originally written in 2002, an= d the first use of
    > _ sync_lock_test_and_set(), for ARM, appeared = in 2012. The commit that
    > made __sync_lock_test_and_set() be chosen auto= matically for platforms
    > that don't specify anything else was added in = 2022.

Thanks for the info.

 

 

 

------------------
    > Ok, if we don't need the assembler code at all, tha= t's good. A patch to
    > introduce AIX support should not change it for= non-AIX powerpc systems
    > though. That might be a good change, but would= need to be justified
    > separately, e.g.  by some performance tes= ting, and should be a separate
    > patch.

    > If you make no changes to s_lock.h at all, will it = work? Why not?

With the existing asm code I se= e there are some syntax errors, being hit.

But after reverting the old cha= nges the issues resolved. Below are diffs.

 

     static= __inline__ int

     tas(vo= latile slock_t *lock)

     {=

    @@ -424,17 += 413,15 @@ tas(volatile slock_t *lock)

     &= nbsp;      __asm__ __volatile__(=

     "=       lwarx   %0,0,%3,1   = ;    \n"

     "=       cmpwi   %0,0   &nbs= p;        \n"

    -" = ;     bne     1f   &= nbsp;           &nbs= p;      \n"

    +" = ;     bne     $+16   = ;         \n"   = ;          /* branch to li %1,= 1 */

     "=       addi    %0,%0,1  &n= bsp;      \n"

     "=       stwcx.  %0,0,%3    =      \n"

    -" = ;     beq     2f   &= nbsp;           &nbs= p;      \n"

    -"1: \n= "

    +" = ;     beq     $+12   = ;         \n"   = ;          /* branch to lwsync= */

     "=       li      %1,1 &= nbsp;          \n"

    -" = ;     b       3f &nb= sp;            =         \n"

    -"2: \n= "

    +" = ;     b       $+12 &= nbsp;          \n" &= nbsp;           /* branch= to end of asm sequence */

     "=       lwsync      &n= bsp;            = ;       \n"

     "=       li      %1,0 &= nbsp;          \n"

    -"3: \n= "

    +=

     : = ;     "=3D&b"(_t), "=3Dr"(_res)= , "+m"(*lock)

     : = ;     "r"(lock)

     : = ;     "memory", "cc");

Let me know if I need to run an= y perf tools to check the performance of

the __sync_lock_test_and_set ch= ange.

 

 

 

---------------

    > > I = mean this part of the code is needed as this is specific to AIX kernel memo= ry
    > > operation which is different from __sync_lock_= test_and_set().
    > >
    > > I would like to mention that the changes = made in src/include/storage/s_lock.h
    > > are pretty much required and need to be operat= ed in assemble specific to IBM
    > > Power architecture.

    > Was that earlier statement incorrect? Is the manual= wrong or outdated or
    > not applicable to us?

Here this change is specific to= AIX, but since we are compiling with gcc, this

is not applicable. But I will t= ry with __sync* routines and check.

 

 

---------------

    > Do you = still need mkldexport.sh? Surely there's a better way to do that=

    > in year= 2024. Some quick googling says there's a '-bexpall' option to

    > 'ld', w= hich kind of sounds like what we want. Will that work? How do

    > other p= rograms do this?

 

Thanks for looking into this, I= =92m working on this, I will let you know.

 

 

Thanks,

Sriram.

 

 

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