Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1t3KyA-00BzWl-MA for pgsql-hackers@arkaria.postgresql.org; Tue, 22 Oct 2024 19:55:06 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.94.2) (envelope-from ) id 1t3Ky9-002nz6-06 for pgsql-hackers@arkaria.postgresql.org; Tue, 22 Oct 2024 19:55:05 +0000 Received: from makus.postgresql.org ([2001:4800:3e1:1::229]) by malur.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1t3Ky8-002nyy-MS for pgsql-hackers@lists.postgresql.org; Tue, 22 Oct 2024 19:55:05 +0000 Received: from mail-io1-xd33.google.com ([2607:f8b0:4864:20::d33]) by makus.postgresql.org with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94.2) (envelope-from ) id 1t3Ky5-002KyF-6V for pgsql-hackers@postgresql.org; Tue, 22 Oct 2024 19:55:03 +0000 Received: by mail-io1-xd33.google.com with SMTP id ca18e2360f4ac-83a9cd37a11so256854339f.3 for ; Tue, 22 Oct 2024 12:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729626900; x=1730231700; darn=postgresql.org; h=content-disposition:mime-version:message-id:subject:cc:to:from:date :from:to:cc:subject:date:message-id:reply-to; bh=ka37y/GQ5RRiSZhkp4J6W9/AGOLO0tXZEKTJOCtkgwM=; b=Ld9q/FWHlSpi31qFoskY6xw0qmg6rKbsNm1/xIk9YAMpZnQsWp6voZNbHPyYg0L5hY /HK+u+du2AwE6mPOTnLevzsqyrtvP/UwECr5nPS5bQYPYrwWVXvlGZGQzh7cO0CllNye 7H7LDOnNjK9vTONM1CS54LTzdn4Byyc3MvvSstT5LsvJ4yIt75HTdgEQPoL1fhEDkUyA kTJs5gdzIlAOMxyuWaoJTTF7bTalcOKPZE0Z9i3rFQsGkTM9EK65VkjQ6Pcvi36we6sa sbqokS6iqygT4WpHwjd3OWnTMY0RG6/1DdKgz3q4AkCgBoCZn+3gV0slT4oSLeYxcRAc 65bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729626900; x=1730231700; h=content-disposition:mime-version:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ka37y/GQ5RRiSZhkp4J6W9/AGOLO0tXZEKTJOCtkgwM=; b=QMJTgZh/qsuR30HeEJZcpOpYEQo2LHtn54dvanO8NMPuEoGPN8YkocBiy6OIC8ItR0 7Y+eXjbEaEc+19GkEfiAYryt7vephVCjJokn/sboW1TBrb9Lk2CTlXN3ssaSyZbiOssZ ToUtAmCQ0Tx3muc3UjZVSkoGnEWlPmOh8sFVTgLTYbu+V0VFn5rGGMapJ4RASipbFuOQ DH6L/EKkmr4NI3acaHATR8hGaLTmUVVWLAwmxysJGBFpuecH6uY1fRR1GwM/QOrwsGlD dnq6bfrpWwfmQCtqKUExc2sOuwNt739ov0GGwlqcyUfroRmYm7HGona0DkNvpgm57Z1N 5Ubw== X-Gm-Message-State: AOJu0YwwC1tX+ujLFVuuQK6Jykd7BNBw4CX7PtUDPirhfurLC9iE3a82 dqJiAL45bKQW9lFNZX01xRV1wpYPziVh3765gbib3/nM4Ujf8f4w5ti2Uw== X-Google-Smtp-Source: AGHT+IGi/2X51PPlwEtPdVMGTqsFVfAS7eHEsng05VL9bnNvThgytrn3G6v8dCyZCgLcu7qc+A+T+w== X-Received: by 2002:a05:6602:6d07:b0:835:46cb:6747 with SMTP id ca18e2360f4ac-83af616a7cbmr46816339f.4.1729626899947; Tue, 22 Oct 2024 12:54:59 -0700 (PDT) Received: from nathan (162-195-168-172.lightspeed.stlsmo.sbcglobal.net. [162.195.168.172]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4dc2a5570e8sm1704470173.59.2024.10.22.12.54.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 12:54:59 -0700 (PDT) Date: Tue, 22 Oct 2024 14:54:57 -0500 From: Nathan Bossart To: pgsql-hackers@postgresql.org Cc: dipiets@amazon.com Subject: use a non-locking initial test in TAS_SPIN on AArch64 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="cHDCaEHhDdnHUGIr" Content-Disposition: inline List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk --cHDCaEHhDdnHUGIr Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline My colleague Salvatore Dipietro (CC'd) sent me a couple of profiles that showed an enormous amount of s_lock() time going to the __sync_lock_test_and_set() call in the AArch64 implementation of tas(). Upon closer inspection, I noticed that we don't implement a custom TAS_SPIN() for this architecture, so I quickly hacked together the attached patch and ran a couple of benchmarks that stressed the spinlock code. I found no discussion about TAS_SPIN() on ARM in the archives, but I did notice that the initial AArch64 support was added [0] before x86_64 started using a non-locking test [1]. These benchmarks are for a c8g.24xlarge running a select-only pgbench with 256 clients and pg_stat_statements.track_planning enabled. without the patch: 90.04% postgres [.] s_lock 1.07% pg_stat_statements.so [.] pgss_store 0.59% postgres [.] LWLockRelease 0.56% postgres [.] perform_spin_delay 0.31% [kernel] [k] arch_local_irq_enable | while (TAS_SPIN(lock)) | { | perform_spin_delay(&delayStatus); 0.12 |2c: -> bl perform_spin_delay | tas(): | return __sync_lock_test_and_set(lock, 1); 0.01 |30: swpa w20, w1, [x19] | s_lock(): 99.87 | add x0, sp, #0x28 | while (TAS_SPIN(lock)) 0.00 | ^ cbnz w1, 2c tps = 74135.100891 (without initial connection time) with the patch: 30.46% postgres [.] s_lock 5.88% postgres [.] perform_spin_delay 4.61% [kernel] [k] arch_local_irq_enable 3.31% [kernel] [k] next_uptodate_page 2.50% postgres [.] hash_search_with_hash_value | while (TAS_SPIN(lock)) | { | perform_spin_delay(&delayStatus); 0.63 |2c:+-->add x0, sp, #0x28 0.07 | |-> bl perform_spin_delay | |while (TAS_SPIN(lock)) 0.25 |34:| ldr w0, [x19] 65.19 | +--cbnz w0, 2c | tas(): | return __sync_lock_test_and_set(lock, 1); 0.00 | swpa w20, w0, [x19] | s_lock(): 33.82 | ^ cbnz w0, 2c tps = 549462.785554 (without initial connection time) [0] https://postgr.es/c/5c7603c [1] https://postgr.es/c/b03d196 -- nathan --cHDCaEHhDdnHUGIr Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="v1-0001-Use-a-non-locking-initial-test-in-TAS_SPIN-on-AAr.patch" From a69b7d38c40f0fb49f714c49bb45c292e7c8587d Mon Sep 17 00:00:00 2001 From: Nathan Bossart Date: Tue, 22 Oct 2024 14:33:39 -0500 Subject: [PATCH v1 1/1] Use a non-locking initial test in TAS_SPIN on AArch64. --- src/include/storage/s_lock.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index e94ed5f48b..07f343baf8 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -270,6 +270,12 @@ tas(volatile slock_t *lock) */ #if defined(__aarch64__) +/* + * On ARM64, it's a win to use a non-locking test before the TAS proper. It + * may be a win on 32-bit ARM, too, but nobody's tested it yet. + */ +#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock)) + #define SPIN_DELAY() spin_delay() static __inline__ void -- 2.39.5 (Apple Git-154) --cHDCaEHhDdnHUGIr--