Received: from malur.postgresql.org ([217.196.149.56]) by arkaria.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1p12gi-000297-Ex for pgsql-hackers@arkaria.postgresql.org; Fri, 02 Dec 2022 09:50:32 +0000 Received: from localhost ([127.0.0.1] helo=malur.postgresql.org) by malur.postgresql.org with esmtp (Exim 4.92) (envelope-from ) id 1p12gh-0000NU-8V for pgsql-hackers@arkaria.postgresql.org; Fri, 02 Dec 2022 09:50:31 +0000 Received: from makus.postgresql.org ([2001:4800:3e1:1::229]) by malur.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1p12gg-0000NL-Tt for pgsql-hackers@lists.postgresql.org; Fri, 02 Dec 2022 09:50:30 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by makus.postgresql.org with esmtps (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p12ga-0005sz-7u for pgsql-hackers@lists.postgresql.org; Fri, 02 Dec 2022 09:50:29 +0000 Received: by mail-wr1-x429.google.com with SMTP id o5so7008376wrm.1 for ; Fri, 02 Dec 2022 01:50:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=MSiY/xvyYl6O86KtWXqU+/Lp91eZdRhAoAdnqKBdNfI=; b=my6gJZQUaFuIg95kx0LgkbQk93ZVRE8O/Zn0Ibv9EWoyt3EQ3nw5IjP2PLkKWq4KMh OLc3cL4K7xvulZf897rJ1k9NdxyCRnNyB73QH2N2kgE4LMZK0AiZ9MynMk/qWLY8b7m2 i+7cwfbJpqNcQI7bx+b+0U4stx+DGIh0aVmo2bsqBnOfP7NugJeK9uO8MsiWOUpVkt0W l0RAChWjbj17rVAj9fdqJZymjsN0nA6xP4EsCQdh5SGpeueyz2kZBHD6siLiwxE4eDrA lYgf2n2j5CuSedJysc0AG4Y5wGS7EnJQIB/dAS0hkyyOfXNYJtLHMhZRyp5mUPT7P4kH oMHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MSiY/xvyYl6O86KtWXqU+/Lp91eZdRhAoAdnqKBdNfI=; b=Y2KO/OSyHTJ9cEhGQmawEJszJh84K7RiZe3j10vmoW98N6qte7yXYO+zXeOfRmbCV/ YAB8IKD5RtZykYL/Yu3d3ZMcL6ZVEkfFlALBCGBK3MbmNKx31injjdz/+oFZNb8YyEIT jaSmv+hCvssibN91pBy9eb/FTHs/XK7+oJxY0j2Krn8sgKu7Kd8dId2/0zXaqSf8Ridq hH7EWBo80NxDX94RpW8V5WvUVtdgbm84NNyDPx59fFlpCofyfCLoagZOETUHCNvw96hA aOO852hDL7S7pEafWgWaOvyGM2NYYHsKtcwfk+b1cCUuUINoIYuZ2DUe1zWzoc/uqiWq B/Vg== X-Gm-Message-State: ANoB5pnmRpkQfoetGulEaVL0yKTjW2Pn5NY/IWEL91wtweBIAr035H/p DlCJ0qyc0mnlQQvD+oQP+4k65Q== X-Google-Smtp-Source: AA0mqf53yC3uZRvL7tp8BcR9rBN2zz/HOAoVdrKdMD0hJF1lNFcRjBBOYzNI3uIe4RyAkgJknUGPXQ== X-Received: by 2002:a5d:4241:0:b0:236:57cf:1b6f with SMTP id s1-20020a5d4241000000b0023657cf1b6fmr31885914wrr.153.1669974622868; Fri, 02 Dec 2022 01:50:22 -0800 (PST) Received: from [192.168.1.166] ([212.228.7.114]) by smtp.gmail.com with ESMTPSA id t16-20020a5d6910000000b0024217e7aaa7sm6450410wru.50.2022.12.02.01.50.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Dec 2022 01:50:22 -0800 (PST) Message-ID: Date: Fri, 2 Dec 2022 09:50:20 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH] Add native windows on arm64 support Content-Language: en-US To: John Naylor Cc: Michael Paquier , Andres Freund , Ian Lawrence Barwick , Tom Lane , Thomas Munro , Julien Rouhaud , PostgreSQL Hackers References: <3886822.1661905738@sss.pgh.pa.us> <20476.1661967233@sss.pgh.pa.us> <271611.1661998926@sss.pgh.pa.us> <20221105183136.hfxyl5dclxdcoyih@awork3.anarazel.de> <7ff7c416-fdfe-517f-a65c-9e5bd8ff8cec@linaro.org> From: Niyas Sait In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: List-Help: List-Subscribe: List-Post: List-Owner: List-Archive: Archived-At: Precedence: bulk On 02/12/2022 05:41, John Naylor wrote: >> I couldn't find something more official for the sse2neon library part. > Not quite sure what this is referring to, but it seems we can just point to > the __aarch64__ section in the same file, which uses the same instruction: > > spin_delay(void) > { > __asm__ __volatile__( > " isb; \n"); > } > > ...and which already explains the choice with a comment. Good point. Will add the comment. > + if cc.get_id() == 'msvc' > + cdata.set('USE_ARMV8_CRC32C', false) > + cdata.set('USE_ARMV8_CRC32C_WITH_RUNTIME_CHECK', 1) > + have_optimized_crc = true > + else > > That seems like a heavy-handed way to force it. Could we just use the same > gating in the test program that the patch puts in the code of interest? > Namely: > > +#ifndef _MSC_VER > #include > +#endif I took a similar approach as x86 MSVC code. I don't think the test program would work with MSVC. The compiler options are not MSVC friendly. -- Niyas