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From: Nathan Bossart <[email protected]>
To: Greg Burd <[email protected]>
Cc: Thomas Munro <[email protected]>
Cc: PostgreSQL Hackers <[email protected]>
Cc: Peter Eisentraut <[email protected]>
Cc: Dave Cramer <[email protected]>
Cc: Andres Freund <[email protected]>
Subject: Re: [PATCH] Fix ARM64/MSVC atomic memory ordering issues on Win11 by adding explicit DMB ?barriers
Date: Fri, 12 Dec 2025 10:03:01 -0600
Message-ID: <aTw8tb_eIpDBYHfW@nathan> (raw)
In-Reply-To: <[email protected]>
References: <CA+hUKG+r5TUe0vvqyFdD4cCpmYOXNso3QJ0whi0Md0YY6xG-Gw@mail.gmail.com>
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+/*
+ * _InterlockedExchange() generates a full memory barrier (or release
+ * semantics that ensures all prior memory operations are visible to
+ * other cores before the lock is released.
+ */
+#define S_UNLOCK(lock) (InterlockedExchange(lock, 0))

This seems to change the implementation from

	#define S_UNLOCK(lock)	\
		do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)

in some cases, but I am insufficiently caffeinated to figure out what
platforms use which implementation.  In any case, it looks like we are
changing it for some currently-supported platforms, and I'm curious why.
Perhaps there's some way to make the #ifdefs a bit more readable, too
(e.g., a prerequisite patch that rearranges things).

The rest looks generally reasonable to me.

-- 
nathan

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