Feedback-ID: id4a34324:Fastmail
Date: Sat, 8 Mar 2025 10:20:55 -0500
From: Andres Freund <andres@anarazel.de>
To: Alexander Korotkov <aekorotkov@gmail.com>
Cc: pgsql-hackers <pgsql-hackers@postgresql.org>
Subject: Re: pg_atomic_compare_exchange_*() and memory barriers
Message-ID: <i6c5gvab3yu6a7ncofixch53b7tkvvwci5scvq6z3eulnkcg7u@4sv7wht4qz4c>
References: <oc4iicdkwyhdf5o5vbwsl7jdlqnds37xtf27wuxvhy3abxoo6i@4ek3xp5j6niy>
 <CAPpHfdvp=_1NRF4YFFp9Oii7mRR5V4b-C2aukbuLQjWMjynYrw@mail.gmail.com>
 <aw3hirtizbn42fkl57bjeafzws3b2bvhknimbxyoi23i43sajb@i65p2ubb6zte>
 <CAPpHfdvp3vNVp5_Rx1RtwLqhjbzzUxwkqzvsh=1E3A+iePvWBg@mail.gmail.com>
 <vwtct75cykxo3rxjipye2bfvkaftncps4ycdock5vbvnwqtte5@h2hklzn36ckm>
 <CAPpHfduxVxkZpCaYRv_whvNyPxCTSyEgXR02sbo=mhGF0MDQEg@mail.gmail.com>
 <CAPpHfdv5y63auGJ_QGJ7VDA1z7cS+YcfUtgAxGit5c2EApbMBA@mail.gmail.com>
 <6ybtypq2v3kvskiqj7izl2rmfrcluilsmbobtpylcnp7moa7vq@2q3cplokvcza>
 <vhimanxfy2h5hlfxeaoxqak4bfdovy35tbrd7o2jq6q5e27mc6@6ntlvt2n3ltk>
 <CAPpHfdtja4qxK5-T+RTdHki+sycbrZaP7==2CD4K+_b+dkUxNA@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: 
 <CAPpHfdtja4qxK5-T+RTdHki+sycbrZaP7==2CD4K+_b+dkUxNA@mail.gmail.com>
Archived-At: 
 <https://www.postgresql.org/message-id/i6c5gvab3yu6a7ncofixch53b7tkvvwci5scvq6z3eulnkcg7u%404sv7wht4qz4c>
Precedence: bulk

Hi,

On 2025-03-08 17:06:38 +0200, Alexander Korotkov wrote:
> On Sat, Mar 8, 2025 at 3:41 PM Andres Freund <andres@anarazel.de> wrote:
> >
> > On 2025-03-08 08:02:41 -0500, Andres Freund wrote:
> > > From the C/C++ standard atomics model it doesn't make sense to say that a
> > > failed CAS has release semantics, as there simply isn't a write that could be
> > > ordered!  What their barriers guarantee is ordering between multiple memory
> > > operation, you can't order multiple writes if you don't have multiple
> > > writes...  The synchronization in the C/C++ model is only established between
> > > accesses of the same variable and there's no write in the case of a failed
> > > CAS, so there's nothing that could establish a release-acquire ordering.
> > >
> > > Unfortunately that model doesn't mesh well with barriers that aren't attached
> > > to read/modify operations. Which is what we ended up with...
> >
> > Adding a full barrier to failed CAS would be a rather large overhead,
> > undesirable in just about any sane algorithm. As a consequence, I think what
> > we ought to do is to redefine the barrier semantics to only imply an acquire
> > barrier in case CAS fails.
> 
> Thank you, I'm good with this solution.  Can I leave this on you?  I'm
> not feeling myself strong to word this correctly.

Not in the next ~four weeks. If you ping me afterwards, I can give it a go.

FWIW, I am fairly certain that any non-toy algorithm that requires a full
memory barrier instead of just an acquire in case of a CAS failure is chock
full of concurrency bugs.

Greetings,

Andres Freund