X-Original-To: pgsql-performance-postgresql.org@localhost.postgresql.org Received: from localhost (mx1.hub.org [200.46.208.251]) by postgresql.org (Postfix) with ESMTP id 4F52E11F60E3 for ; Fri, 28 Apr 2006 05:49:31 -0300 (ADT) Received: from postgresql.org ([200.46.204.71]) by localhost (mx1.hub.org [200.46.208.251]) (amavisd-new, port 10024) with ESMTP id 17824-07 for ; Fri, 28 Apr 2006 05:49:18 -0300 (ADT) X-Greylist: delayed 00:16:49.751071 by SQLgrey- Received: from svr4.postgresql.org (svr4.postgresql.org [66.98.251.159]) by postgresql.org (Postfix) with ESMTP id 36DFD11F609E for ; Fri, 28 Apr 2006 05:49:17 -0300 (ADT) Received: from mail.aeccom.com (port-83-236-156-26.static.qsc.de [83.236.156.26]) by svr4.postgresql.org (Postfix) with ESMTP id 227805B6482 for ; Fri, 28 Apr 2006 08:32:25 +0000 (GMT) Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.aeccom.com (Postfix) with ESMTP id 9D36D1C4E7; Fri, 28 Apr 2006 10:32:21 +0200 (CEST) Received: from mail.aeccom.com ([127.0.0.1]) by localhost (gate6.aeccom.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 16945-01-3; Fri, 28 Apr 2006 10:32:20 +0200 (CEST) Received: from [192.168.2.14] (andes.core.aeccom.com [192.168.2.14]) by mail.aeccom.com (Postfix) with ESMTP id 7F8DB1C49A; Fri, 28 Apr 2006 10:32:20 +0200 (CEST) Message-ID: <4451D310.7010701@aeccom.com> Date: Fri, 28 Apr 2006 10:32:16 +0200 From: Sven Geisler Organization: AEC/communications GmbH User-Agent: Thunderbird 1.5.0.2 (Windows/20060308) MIME-Version: 1.0 To: Vivek Khera Cc: Pgsql performance Subject: Re: Large (8M) cache vs. dual-core CPUs References: <20060425141435.6c8c163c.wmoran@collaborativefusion.com> <3EF41DD8-1073-4EAC-B6D7-4A78BE7549F8@khera.org> In-Reply-To: <3EF41DD8-1073-4EAC-B6D7-4A78BE7549F8@khera.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: amavisd-new at aeccom.com X-Virus-Scanned: Maia Mailguard 1.0.1 X-Archive-Number: 200604/664 X-Sequence-Number: 18748 Hi all, Vivek Khera schrieb: > On Apr 25, 2006, at 2:14 PM, Bill Moran wrote: >> Where I'm stuck is in deciding whether we want to go with dual-core >> pentiums with 2M cache, or with HT pentiums with 8M cache. > > In order of preference: > > Opterons (dual core or single core) > Xeon with HT *disabled* at the BIOS level (dual or single core) > > > Notice Xeon with HT is not on my list :-) > I support Vivek's order of preference. I have been going through a nightmare of performance issues with different x86 hardware. At the end of the day I can say the Opterons are faster because of their memory bandwidth. I also had to disable HT on all our customers servers which were still using XEON's with HT. There is a paper from HP which describes the advantage of the memory architecture of the Opterons. This is the best explanation to me why Opteron 875 is faster than a XEON MP 3 GHz, which I did compare last year. I remember a thread in the postgresql devel list around HT in 2004, where you can find the reason why you should disable HT. This thread refers to Intel Developer Manual Volume 4 (Architecture Optimisation) where there is some advice regarding spin-wait loop. This is related to the code of src/include/storage/s_lock.h. Cheers Sven. ====== From Intel Developer Manual Volume 4 Synchronization for Short Periods The frequency and duration that a thread needs to synchronize with other threads depends application characteristics. When a synchronization loop needs very fast response, applications may use a spin-wait loop. A spin-wait loop is typically used when one thread needs to wait a short amount of time for another thread to reach a point of synchronization. A spin-wait loop consists of a loop that compares a synchronization variable with some pre-defined value [see Example 7-1(a)]. On a modern microprocessor with a superscalar speculative execution engine, a loop like this results in the issue of multiple simultaneous read requests from the spinning thread. These requests usually execute out-of-order with each read request being allocated a buffer resource. On detection of a write by a worker thread to a load that is in progress, the processor must guarantee no violations of memory order occur. The necessity of maintaining the order of outstanding memory operations inevitably costs the processor a severe penalty that impacts all threads. This penalty occurs on the Pentium Pro processor, the Pentium II processor and the Pentium III processor. However, the penalty on these processors is small compared with penalties suffered on the Pentium 4 and Intel Xeon processors. There the performance penalty for exiting the loop is about 25 times more severe. On a processor supporting Hyper-Threading Technology, spin-wait loops can consume a significant portion of the execution bandwidth of the processor. One logical processor executing a spin-wait loop can severely impact the performance of the other logical processor. ====