From: Andres Freund <andres@anarazel.de>
To: Tom Lane <tgl@sss.pgh.pa.us>
Cc: Robert Haas <robertmhaas@gmail.com>
Cc: pgsql-hackers@lists.postgresql.org
Subject: Re: Atomic operations within spinlocks
Date: Fri, 5 Jun 2020 20:32:32 -0700
Message-ID: <20200606033232.4lsf4g3l67cq2bw7@alap3.anarazel.de> (raw)
In-Reply-To: <1647173.1591411967@sss.pgh.pa.us>
References: <1141819.1591208385@sss.pgh.pa.us>
<20200603204542.reuladbmgmjqzoi6@alap3.anarazel.de>
<1253593.1591293439@sss.pgh.pa.us>
<20200604185525.wuyjtkluppj4eddr@alap3.anarazel.de>
<1256701.1591297654@sss.pgh.pa.us>
<20200605023302.g6v3ydozy5txifji@alap3.anarazel.de>
<20200606001926.zin5getvvhqppnm2@alap3.anarazel.de>
<1642804.1591405316@sss.pgh.pa.us>
<20200606023103.avzrctgv7476xj7i@alap3.anarazel.de>
<1647173.1591411967@sss.pgh.pa.us>
Hi,
On 2020-06-05 22:52:47 -0400, Tom Lane wrote:
> Andres Freund <andres@anarazel.de> writes:
> > On 2020-06-05 21:01:56 -0400, Tom Lane wrote:
> >> At some point I think we'll have to give up --disable-spinlocks; it's
> >> really of pretty marginal use (how often does anyone port PG to a new
> >> CPU type?) and the number of weird interactions it adds in this area
> >> seems like more than it's worth.
>
> > Indeed. And any new architecture one would port PG to would have good
> > enough compiler intrinsics to make that trivial. I still think it'd make
> > sense to have a fallback implementation using compiler intrinsics...
>
> > And I think we should just require 32bit atomics at the same time. Would
> > probably kill gaur though.
>
> Not only gaur. A quick buildfarm survey finds these active members
> reporting not having 32-bit atomics:
Hm, I don't think that's the right test. We have bespoke code to support
most of these, I think:
> anole | 2020-06-05 11:20:17 | pgac_cv_gcc_atomic_int32_cas=no
Has support via acc specific intrinsics.
> chipmunk | 2020-05-29 22:27:56 | pgac_cv_gcc_atomic_int32_cas=no
Doesn't have support for __atomic, but does have support for 32bit
__sync.
> gharial | 2020-06-05 12:41:14 | pgac_cv_gcc_atomic_int32_cas=no
__sync support for both 32 and 64 bit.
> curculio | 2020-06-05 22:30:06 | pgac_cv_gcc_atomic_int32_cas=no
> frogfish | 2020-05-31 13:00:25 | pgac_cv_gcc_atomic_int32_cas=no
__sync support for both 32 and 64 bit.
> mandrill | 2020-06-05 09:20:03 | pgac_cv_gcc_atomic_int32_cas=no
__sync support for 32, as well as as inline asm for 32bit atomics
(although we might be able to add 64 bit).
> hornet | 2020-06-05 09:11:26 | pgac_cv_gcc_atomic_int32_cas=no
> hoverfly | 2020-06-05 22:06:14 | pgac_cv_gcc_atomic_int32_cas=no
__sync support for both 32 and 64 bit, and we have open coded ppc asm.
> locust | 2020-06-05 10:14:29 | pgac_cv_gcc_atomic_int32_cas=no
> prairiedog | 2020-06-05 09:55:49 | pgac_cv_gcc_atomic_int32_cas=no
Wee, these don't have __sync? But I think it should be able to use the
asm ppc implementation for 32 bit atomics.
> gaur | 2020-05-19 13:33:25 | pgac_cv_gcc_atomic_int32_cas=no
As far as I understand pa-risc doesn't have any atomic instructions
except for TAS.
So I think gaur is really the only one that'd drop.
> It looks to me like this is mostly about compiler support not the
> hardware; that doesn't make it not a problem, though. (I also
> remain skeptical about the quality of the compiler intrinsics
> on non-mainstream hardware.)
I think that's fair enough for really old platforms, but at least for
gcc / clang I don't think it's a huge concern for newer ones. Even if
not mainstream. For gcc/clang the intrinsics basically back the
C11/C++11 "language level" atomics support. And those are extremely
widely used these days.
Greetings,
Andres Freund
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To: pgsql-hackers@postgresql.org
Cc: andres@anarazel.de, tgl@sss.pgh.pa.us, robertmhaas@gmail.com, pgsql-hackers@lists.postgresql.org
Subject: Re: Atomic operations within spinlocks
In-Reply-To: <20200606033232.4lsf4g3l67cq2bw7@alap3.anarazel.de>
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