From: mark@mark.mielke.cc
To: Jim C. Nasby <jnasby@pervasive.com>
Cc: Bruce Momjian <pgman@candle.pha.pa.us>
Cc: Scott Marlowe <smarlowe@g2switchworks.com>
Cc: Bill Moran <wmoran@collaborativefusion.com>
Cc: pgsql-performance@postgresql.org
Subject: Re: Large (8M) cache vs. dual-core CPUs
Date: Wed, 26 Apr 2006 22:56:02 -0400
Message-ID: <20060427025602.GA19089@mark.mielke.cc> (raw)
In-Reply-To: <20060426223731.GE97354@pervasive.com>
References: <20060426220929.GY97354@pervasive.com>
<200604262216.k3QMGkk15952@candle.pha.pa.us>
<20060426223731.GE97354@pervasive.com>
On Wed, Apr 26, 2006 at 05:37:31PM -0500, Jim C. Nasby wrote:
> On Wed, Apr 26, 2006 at 06:16:46PM -0400, Bruce Momjian wrote:
> > AMD transfers the dirty cache line directly from cpu to cpu. I can
> > imaging that helping our test-and-set shared memory usage quite a bit.
> Wasn't the whole point of test-and-set that it's the recommended way to
> do lightweight spinlocks according to AMD/Intel? You'd think they'd have
> a way to make that performant on multiple CPUs (though if it's relying
> on possibly modifying an underlying data page I can't really think of
> how to do that without snaking through the cache...)
It's expensive no matter what. One method might be less expensive than
another. :-)
AMD definately seems to have things right for lowest absolute latency.
2X still sounds like an extreme case - but until I've actually tried a
very large, or thread intensive PostgreSQL db on both, I probably
shouldn't doubt the work of others too much. :-)
Cheers,
mark
--
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To: pgsql-performance@postgresql.org
Cc: mark@mark.mielke.cc, jnasby@pervasive.com, pgman@candle.pha.pa.us, smarlowe@g2switchworks.com, wmoran@collaborativefusion.com
Subject: Re: Large (8M) cache vs. dual-core CPUs
In-Reply-To: <20060427025602.GA19089@mark.mielke.cc>
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